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Astera Labs is seeking a Senior Physical Design Engineer to join their high-performance design team working on next-generation transceiver IPs targeting TSMC 5nm and 3nm technology nodes. The role involves ownership of physical implementation from RTL to GDSII, ensuring timing and power closure for ultra-high-speed designs.
Astera Labs is seeking a Principal Integrated Circuit Designer to join their SerDes team in Singapore. The role involves designing sophisticated advanced node CMOS products, including high-speed mixed-signal circuits and analog ICs. Candidates must have a Master’s or PhD in EE with 6+ years of experience in complex analog IC designs.
Senior Integrated Circuit Designer role at Astera Labs in Singapore. Involves designing advanced node CMOS products, layout development, and test programs for connectivity applications. Requires Master’s or PhD in EE and experience with high-speed mixed-signal circuits.