Astera Labs

Astera Labs is seeking a Director of System Validation Engineering to build and scale their validation organization for AI infrastructure products. The role requires 12+ years of experience in silicon validation and leadership skills. Candidates will develop validation plans and engage with key customers.

Astera Labs seeks a Firmware Engineering Director/Manager to lead firmware development for SoC and systems products in data-center and AI infrastructure. The role involves technical direction, people leadership, and execution across core firmware, bare-metal software, and device drivers. Candidates need 10+ years of experience in firmware development and 5+ years in management.

Astera Labs is seeking a Senior Software Diagnostics Engineer to build diagnostics and manufacturing software for high-speed datacenter products. The role involves working on projects from conception to production, focusing on design validation or automation/manufacturing. Candidates need a strong software background and understanding of hardware design.

Astera Labs is seeking an experienced Hardware Lab Engineer to develop connectivity products for AI infrastructure. The role supports silicon bring-up, characterization, and debug activities through hands-on lab execution. Candidates require deep circuit understanding and experience with high-speed interfaces like PCIe and CXL.

Astera Labs is seeking a Lead Lab Validation Engineer in San Jose, CA to root-cause customer quality concerns and develop corrective actions. The role involves debugging high-speed link failures, analyzing retimer issues, and utilizing advanced lab instrumentation. Candidates require 10+ years of experience with PCIe protocol and electrical engineering expertise.

Astera Labs is seeking a Manager, Package Design Engineering to lead and scale their Package Design team in San Jose. This role involves owning end-to-end delivery of advanced IC packaging solutions for AI infrastructure and connectivity products. The candidate will build a high-performing team while driving cross-functional execution with silicon architecture and manufacturing partners.

Astera Labs seeks a Physical Design/CAD Engineer to support connectivity ASIC design. The role involves RTL to GDS ownership across Synthesis, PnR, STA, and Signoff. Candidates will collaborate with RTL and verification teams for robust full-chip signoff.

Astera Labs seeks a Principal Design Verification Engineer to lead verification strategies for next-generation AI connectivity ASICs. The role requires ownership of the full verification lifecycle using SystemVerilog, UVM, and hybrid methodologies for protocols like PCIe Gen 6/7 and CXL. Candidates must possess 10+ years of experience verifying complex SoCs and strong leadership skills.

Astera Labs is seeking a Principal Design Verification Engineer to lead functional verification of advanced ASICs for server and networking applications. The role requires expertise in SystemVerilog/UVM, C/C++, and Python, along with 8+ years of experience in SoC verification. Candidates will drive verification strategy, debug test failures, and collaborate with software teams on emulation platforms.

Astera Labs is seeking a Principal Digital Design Engineer for their DSP SerDes team in San Jose, CA. The role involves developing advanced high-speed SerDes wireline and optical transceivers for AI systems. Candidates must have 5-10 years of experience in digital design and proficiency in System Verilog.

Astera Labs seeks a Principal Digital Design Engineer to architect next-generation digital designs for high-performance connectivity solutions. This role requires owning complex blocks from micro-architecture through silicon bring-up with 8+ years of SoC experience. Candidates must possess expertise in RTL coding, timing closure, and high-speed protocols.

Astera Labs is seeking a Principal Electronics Engineer for their Hardware Electrical Validation team in San Jose, CA. The role involves de-risking circuits, developing validation plans, and debugging complex hardware failures. Candidates need 10+ years of experience in hardware test or design.

Astera Labs seeks a Principal Embedded Software Engineer to develop firmware for Ethernet retimers and gearboxes in their Taurus product line. This on-site role in San Jose involves managing complex system integration, SERDES configuration, and link training sequences for AI infrastructure connectivity solutions. The ideal candidate will have 10+ years of embedded C/C++ experience and strong debugging skills.

Astera Labs seeks a Principal Emulation Engineer to verify protocols on complex ASICs and develop emulation environments. The role requires 8+ years of experience in SoC/silicon product development and knowledge of protocols like PCIe and DDR. Candidates must be authorized to work in the US and able to relocate to San Jose, CA.

Astera Labs is seeking a Principal Firmware Engineer to architect and develop firmware and microcontroller subsystems for their SoC and systems products. The role requires extensive experience in electrical engineering, embedded firmware development, and high-speed interfaces like PCIe and Ethernet. Candidates must have a strong background in C/C++ and Python, along with 8+ years of experience in server, storage, or networking applications.

Astera Labs is seeking a Principal Firmware Engineer to architect and develop firmware and microcontroller subsystems for their SoC and systems products. The role requires extensive experience with PCIe protocols, C/C++, and embedded firmware development within server, storage, or networking applications. Candidates must have a strong background in electrical engineering and at least 8 years of relevant industry experience.

Astera Labs is seeking a Principal Physical Design Engineer to drive planning and execution for connectivity ASICs used by leading cloud providers. The role requires RTL to GDS ownership across design stages including Synthesis, PnR, STA, and Signoff. Candidates must have over 10 years of experience in PnR and sign-off for complex SoCs.

Astera Labs is seeking a Principal Physical Design Engineer (STA) to drive timing closure and coordination for connectivity ASICs. This role requires end-to-end STA ownership, deep technical expertise, and collaboration with RTL and physical design teams. The position is fully on-site in San Jose, CA.

Astera Labs is hiring a Principal Power and Board Design Engineer in San Jose, CA. The role focuses on designing power delivery systems for ASIC products and requires 8-10 years of experience. The position offers a base salary between $209,000 and $230,000.

Astera Labs is seeking a Principal Product Applications Engineer to join their Aries PCIe Retimer team. This role serves as a technical bridge between customers and engineering, focusing on high-speed PCIe connectivity for AI infrastructure. Responsibilities include customer technical engagement, system-level debugging, and creating technical documentation.

Astera Labs is seeking a Principal Product Applications Engineer to join their Taurus Ethernet Smart Cable Modules team. This role involves driving customer success, debugging physical layer challenges, and ensuring seamless product integration for AI infrastructure connectivity. Candidates must have deep Ethernet expertise and experience with hyperscalers or OEMs.

Astera Labs is seeking a Principal Product Manager for their Ethernet portfolio in San Jose, CA. The role involves defining product requirements, leading planning, and engaging with customers for the Taurus Ethernet Retimer products. Candidates need deep understanding of high-speed protocols and 10+ years of experience in semiconductor product management.

Astera Labs is seeking a Principal Product Manager for Smart Cable Modules in San Jose. This role involves defining product strategy, engaging with hyperscalers, and leading cross-functional teams to deliver high-bandwidth connectivity solutions for AI infrastructure.

Astera Labs seeks a Principal Signal and Power Integrity Engineer to support AI infrastructure connectivity products. Responsibilities include SI planning, design, modeling, simulation, and lab validation. Candidates require 8+ years of experience in high-speed SI/PI design and electrical engineering background.

Astera Labs seeks a Principal Silicon Validation Engineer to develop and execute electrical validation tests for AI connectivity products. The role involves defining validation plans, automating testing, and ensuring robust, production-ready designs for server and networking applications. Candidates require 10+ years of experience in SoC/silicon products and expertise in high-speed interfaces like PCIe and Ethernet.

Astera Labs seeks a Principal System Validation Engineer to validate AI infrastructure connectivity solutions using advanced Data Center equipment. The role requires 8-12 years of experience in electrical engineering and expertise in SerDes protocols like Ethernet and PCIe. Responsibilities include automating testing, designing experiments, and collaborating with customers.

Astera Labs seeks a Principal Test Engineer to lead ATE Test solutions for complex mixed-signal silicon SoC products. The role involves developing test strategies, overseeing manufacturing partners, and managing products from design through high-volume production. Candidates need strong experience with high-speed protocols like PCIe, Ethernet, and Infiniband.

Astera Labs is seeking a Senior DevOps Engineer to join their Silicon Engineering Infrastructure team. The role involves building and optimizing cloud-based infrastructure on AWS to support semiconductor design workflows. Candidates must have strong problem-solving skills and experience with AWS services, automation, and CI/CD pipelines.

Astera Labs is hiring a Senior Digital Design Engineer to design next-generation digital designs for high-performance connectivity solutions. The role involves owning RTL implementation from micro-architecture through sign-off and collaborating with verification and PD teams. Candidates need expertise in SystemVerilog, ASIC flows, and protocols like PCIe or Ethernet.

Astera Labs is hiring a Senior Director System Validation Engineer to lead their AI Fabric Validation organization in San Jose, CA. The role focuses on building a world-class validation team for silicon, firmware, and system-level solutions. Candidates need 15+ years of experience in SoC products and high-performance computing.

Astera Labs is seeking Senior to Senior Principal Firmware Engineers to architect and develop core firmware for next-generation connectivity, chiplet, and system products. The role involves working closely with Architecture, RTL, and Validation teams on embedded microcontrollers and high-speed connectivity protocols like PCIe and CXL. This is an onsite position in San Jose, CA, offering a base salary range of $135,000–$255,000 USD.

Astera Labs seeks a Senior Power BI Developer with 5+ years of experience to design and maintain enterprise-grade dashboards and semantic data models. The role involves collaborating with stakeholders to deliver scalable BI solutions and requires advanced DAX and SQL skills.

Astera Labs is hiring a Senior Principal Digital Design Engineer to lead architecture and implementation of next-generation digital designs for AI infrastructure connectivity. This role involves defining micro-architecture strategies, owning complex chip-level design decisions, and guiding blocks from concept through silicon bring-up. Candidates must have 12+ years of experience in SoC/silicon product development.

Senior Principal System Validation Engineer role at Astera Labs focusing on system validation tests using data center equipment. Responsibilities include developing validation plans, automating testing, and working with customers on connectivity solutions for AI applications.

Astera Labs seeks a Senior Principal Validation Engineer to lead post-silicon validation and characterization for mixed-signal design teams. The role involves developing test methodologies, driving hands-on lab work, and collaborating with cross-functional teams to ensure product reliability. Candidates require deep expertise in mixed-signal systems, high-speed signaling, and automation tools.

Astera Labs is seeking a Senior Silicon Validation Engineer to develop and execute electrical validation tests for DDR memory connectivity products. The role involves formulating validation plans, automating IC testing, and ensuring product robustness for AI/ML applications. Candidates need strong background in Electrical Engineering and experience with high-speed design blocks.

Astera Labs is seeking a Senior SoC Verification/Validation Engineer in San Jose, CA to validate complex SoCs for AI connectivity. The role involves working on industry-leading emulation platforms with a focus on high-speed serial interfaces like PCIe and Ethernet. Candidates must have 5+ years of experience in pre-silicon verification and proficiency in System Verilog, C/C++, and Python.

Astera Labs seeks a Senior/Staff Physical Design Engineer to oversee planning and execution for connectivity ASICs. The role requires 3+ years of experience with backend tools and methodologies for 7nm or less technologies. This fully on-site position is located in San Jose, CA.

Astera Labs is seeking a Senior or Staff System Validation Engineer to develop and perform system validation tests for AI fabric switches. The role involves understanding performance requirements, formulating validation plans, and working directly with customers. Candidates need a strong background in Electrical/Computer Engineering and experience with high-speed protocols like PCIe, CXL, or Ethernet.

Astera Labs seeks a Senior/Tech Lead Post-Silicon Validation Engineer to develop and execute electrical validation tests for AI connectivity products. Responsibilities include formulating validation plans, automating IC testing, and ensuring specification compliance. Candidates require a strong background in Electrical Engineering and experience with high-speed IO/SerDes interfaces.

As a Sr. Principal DSP Architect, you will lead the definition and development of next-generation Digital Signal Processing (DSP) architectures focusing on high-speed PAM4 systems and optical transceivers. You will bridge theoretical communications theory and silicon implementation for 800G, 1.6T, and beyond.

Astera Labs is seeking a Sr. Principal Product Manager for their Leo Smart Memory Controller product line. The role involves defining product requirements, leading customer technical engagement, and supporting go-to-market strategies within the semiconductor industry. Based in San Jose, CA or Vancouver, BC, this position requires in-person presence and travel.

Astera Labs is hiring a Sr. Principal Product Manager for the Scorpio Smart Fabric Switch portfolio in San Jose, CA. The role focuses on defining product requirements, leading customer engagement, and supporting go-to-market strategies for AI infrastructure solutions. Candidates require 10+ years of experience in semiconductor product management.

Astera Labs is seeking a Technical Lead Design Verification Engineer to join their ASIC Engineering team in San Jose. The role involves functional verification of complex ASICs using System Verilog, C, C++, and Python. Candidates must have 5+ years of experience verifying SoCs for Server, Storage, and Networking applications.

Astera Labs is seeking a Technical Lead Power Engineer to design and optimize power delivery systems for ASIC products. The role involves developing high-efficiency circuits, ensuring power integrity, and collaborating with cross-functional teams. Candidates need 5-8 years of experience in power and board design engineering.

Astera Labs is hiring a Technical Lead Product Engineer in San Jose, CA. This role involves leading next-generation high-speed semiconductor product development. Candidates need 5+ years of experience in post-silicon product development, RF testing, and ATE platforms.

Astera Labs is seeking a Technical Lead Product Engineer to lead next-generation high-speed semiconductor products. The role requires 5+ years of experience in post-silicon product development, specifically with high-speed XCVR and PCIe Gen3+. Candidates must have strong problem-solving skills and ATE platform experience.

Astera Labs is establishing a strategic R&D center in Israel and seeking a Physical Design CAD Lead to build local engineering capabilities. The role involves designing automated flows for Synthesis, Place & Route, and Floor-planning while supporting the PD team in optimizing Power, Performance, and Timing. Candidates need expertise in Tcl, Python, and back-end industrial tool suites like Synopsys Fusion Compiler or Cadence Genus.

Astera Labs is seeking a Physical Design Engineer to join their new R&D center in Israel. The role involves leading physical implementation, signoff, and methodology development for AI infrastructure semiconductor chips. Candidates should have experience with RTL2GDS flows and advanced process technologies.

Astera Labs is seeking a Staff/Principal Design Engineer to establish a strategic R&D center in Israel. This role involves designing complex semiconductor chips and digital blocks for AI infrastructure connectivity. Candidates will own the journey from high-level definition through RTL implementation and backend support.